CST 334 - Week 4

This week, I learned about how translation-lookaside buffer (TLB) is used in address translation. TLB is a hardware cache implemented as an associative cache  maintained to speed the process of look-ups. Despite it having the ability to be rather useful, it is only as good as the data it contains. If an VPN of the virtual address being searched for is not within the TLB contents, then it will miss the search until that data is stored. It the data is not within the cache, then it will be retrieved from the page table instead. That data that is selected to be cached are determined by how often they are accessed. I also learned how to calculate the number of bits required for the  VPN and how many bits are the offset.

I also learned about the process of swapping, where the most important pages are selected to be stored in the physical memory. This is how to address the issue of running out of memory space. To help this process, a present bit is utilized in the page table to represent whether or not a page exists in memory. If the virtual page is not present, a page fault is raised by the hardware. The page fault handler will then locate the disk address of the page from the table to fetch into memory. It then updates the page table and marks it as present before trying to execute the instruction again. How a process is selected to be swapped is dependent on the policy selected. For example, FIFO is a policy that can be used, where the oldest cache element will be swapped.